WACI (Wild and Crazy Ideas) Session

Talk	Speaker
Title: How to Succeed at Memory Safety Without Really Trying Abstract: The most important security benefit of software memory safety is easy to state: for C/C++ software, attackers can exploit most bugs and vulnerabilities to gain full, arbitrary control of software behavior, whereas this is not true for most bugs in memory-safe software. Fortunately, this security benefit—most bugs don’t give attackers full control—can be had for unmodified C/C++ software, without per-application effort. This doesn’t require trying to establish memory safety; instead, it is sufficient to eliminate most of the combinatorial ways in which software with corrupted memory can execute. To eliminate these interleavings, there already exist practical compiler and runtime mechanisms that incur little resource overhead and need no special hardware or platform support.	Ulfar Erlingsson (Google)
Title: High Throughput Inter-Continental Communication Abstract: Moving large swaths of data has never been more important. As compute latency becomes increasingly dominated by data movement times, research has focussed on how to reduce these costs. These data movement costs occur on every level of the hardware stack, from moving data between cores to moving physical SSDs between racks in data centers. Yet one domain remains unexplored, how to move data between continents with high bandwidth and low latency. Undersea cables, while cost effective and low latency, limit bandwidth. While the physical data could be moved via plane or ship, latency would be high and data (if the amount is sufficiently large) would be impractical to store on the ship. Now more than ever, novel ways to transmit data across long distances are needed. We take lessons from recent work on near data computing to devise a new solution, showing that we can transform our data movement problem into a rocketry problem. We explain how this solution has far higher bandwidth than existing solutions while providing security guarantees, ultimately proving that it isn’t computer science we should be advancing, it’s rocket science.	Guy Wilks, Jennifer Brana, Nathan Serafin, Nathan Beckmann, Brandon Lucia (Carnegie Mellon University)
Title: Relativistic Hardware Design – Exploring the time space tradeoff Abstract: As a community, we are very good at making large circuits that compute things very quickly. However, sometimes a small and efficient circuit is more desirable, and this is something that is less well explored at ASPLOS. To take this idea to its logical conclusion we built a circuit consisting only of a single time multiplexed NAND gate. The circuit can emulate any digital hardware using very little space, though it is of course predictably slow.	Frans Skarman (Linköping University)
Title: HaHa: Post-Earth Habitat Hardware Co-Design for Computing in Space Abstract: Whether it is a dream coming true or karma, humans leaving Earth and settling in space seems more like a matter of ‘when’ rather than ‘if’. Furthermore, if research studies in space habitation hold any indication, self-sustaining space habitats might be our future homes. These new homes, called space habitats, are massive structures built in space that are designed to accommodate our basic physiological needs: air, water, food, and shelter in an Earth-like environment. However, looking at our dependence on ICT today, a personal computing model in these habitats is equally necessary. To address this, we first identify key constraints for computational systems in these self-sustaining space habitats. Next, considering these constraints and the needs of habitants, we propose ‘HaHa,’ our solution to this problem. ‘HaHa’ is a centralized computational model with a scheduling algorithm suitable for personal computational needs in post-earth space habitats.	Pratiksha Mundhe, Aalaa M.A. Babai (Kyushu University)
Title: Incentivizing Side-Channel Freedom with Leakage-Aware Computation Abstract: Microarchitectural side-channels have long been studied as an interesting security problem. While recent advances have demonstrated the danger and practicality of microarchitectural side-channels, practical systems continually rely on ad hoc mitigations rather than systematic approaches. Instead of searching through system design space, we make microarchitectural side-channel leakage tangible to victims with leakage-aware computation, thereby incentivizing the progress of the search to achieve side-channel freedom. In this paper, we argue that leakage-aware computation is both feasible and practical by tackling cache-based side-channel leakage as a first step.	Gongqi Huang, Jingyuan Chen, Amit Levy (Princeton University)
Title: One for All Chip Abstract: The semiconductor industry is at a crossroads. With Moore’s Law hitting a limit, chip area reaching a constant size, and the cost of designing and fabricating new chips soaring, the traditional approach of building new chips for every generation (e.g., Zen1, Zen2, Zen3) as well as separate chips for different use cases—CPUs for general-purpose tasks, GPUs for graphics and AI, NPUs for machine learning, and DPUs for data processing— is becoming increasingly unsustainable. Every new chip generation demands massive investments in R&D, manufacturing, all while contributing to electronic waste and increasing energy consumption. Yet, at their core, these chips share many architectural similarities. The question we must ask is: Do we really need to build entirely new chips for every slight architectural change? This work challenges the status quo by proposing a fundamentally new paradigm: One for All Chip, a single, highly modular and reconfigurable processor that can adapt dynamically to different use cases, architectures, and performance needs on demand. By moving away from rigid designs and toward a flexible, reconfigurability-driven approach, we can extend chip usability, reduce costs, and build a more sustainable computing future. Furthermore, this approach enables fine-grained power control across different regions of the chip, maximizing energy efficiency by powering down unused components dynamically.	Nitesh Narayana GS (UPC Barcelona), Xavier Martorell (UPC Barcelona)